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AC-link Interface Audio DAC
DESCRIPTION
The WM9709 is a low cost, high-quality stereo audio DAC. It utilises the Intel specified AC-link audio interface protocol, allowing a pair of audio output channels to be added to any AC link compliant controller device at minimal board area and external component cost. The WM9709 device supports 48ks/s sample rates when operated at the normal AC link rate. The WM9709 supports a revision 1.03 AC '97 AC-link interface, the device acting as a master in normal operation. The ID pin can be used to select which data slots on the AC-link are to be used as input to the DAC. This allows 3 x WM9709 to be used with a single controller that supports 6 channel sound, to output surround sound audio signals. When supporting surround, centre or LFE channels, the WM9709 behaves as a slave device. The WM9709 device is footprint compatible with the WM9708 codec, allowing simple swapping between DAC and full codec features on the same board. The WM9709 is packaged in a 20-pin SSOP.
WM9709
FEATURES
* * 20-Bit Stereo DAC Audio Performance - 102dB SNR (`A' weighted at 48kHz) - -95dB THD Revision 1.03 or higher AC'97 AC-link interface support. 3.3V or mixed 3V digital, 5V analogue operation 20-Pin SSOP Package Minimal external component cost Support for surround and centre/LFE channels
* * * * *
APPLICATIONS
* * * * Notebook PC PC sound cards Motherboards Custom sound applications
BLOCK DIAGRAM
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WM9709
ID RESETB SDATAOUT SDATAIN BITCLK SYNC SERIAL INTERFACE SIGMA DELTA MODULATOR DIGITAL FILTERS SIGMA DELTA MODULATOR LEFT DAC LOW PASS FILTER LINEOUTL RIGHT DAC LOW PASS FILTER LINEOUTR
CAP
XTLIN XTLOUT
DVDD DGND
AVDD AGND
AGND
WOLFSON MICROELECTRONICS plc w :: www.wolfsonmicro.com
Production Data, February 2003, Rev 1.3 Copyright 2003 Wolfson Microelectronics plc
WM9709 PIN CONFIGURATION
RESETB ID DVDD XTLIN XTLOUT SDATAOUT BITCLK DGND SDATAIN SYNC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AGND AVDD NC
Production Data
ORDERING INFORMATION
DEVICE WM9709CDS WM9709CDS/R
LINEOUTR LINEOUTL NC CAP NC NC AGND
TEMP. RANGE 0o to 70oC 0o to 70oC
PACKAGE 20-pin SSOP 20-pin SSOP Tape and Reel 330mm Reel 16mm wide tape 2000 units/reel
PIN DESCRIPTION
PIN 1 2 ID NAME RESETB TYPE Digital input Digital input DESCRIPTION NOT reset input (active low, resets digital circuitry) AC link Data slot select. Low = Normal stereo (slots 3,4), High = Surround (slots 7,8), High impedance (Z) = LFE and centre (slots 6,9) Digital positive supply Clock crystal connection or clock input (XTAL not used) Clock crystal connection Serial data input Serial interface clock output to AC-link controller if ID pin held low (WM9709 is master). Serial interface clock input from AC-link master if ID pin held either high or high impedance (WM9709 is slave). Digital ground supply Serial data output to AC-link controller Serial interface sync pulse from AC-link controller Analogue ground supply, chip substrate No internal connection No internal connection Analogue input Analogue output Analogue output Supply Supply Reference input/output; internal divider generates midrail No internal connection Main analogue output for left channel Main analogue output for right channel No internal connection Analogue positive supply Analogue ground supply, chip substrate
3 4 5 6 7
DVDD XTLIN XTLOUT SDATAOUT BITCLK
Supply Digital input Digital output Digital input Digital output (master) Or digital input (slave)
8 9 10 11 12 13 14 15 16 17 18 19 20
DGND SDATAIN SYNC AGND NC NC CAP NC LINEOUTL LINEOUTR NC AVDD AGND
Supply Digital output Digital input Supply
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Production Data
WM9709
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.
CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Operating temperature range, TA Storage temperature prior to soldering Storage temperature after soldering Package body temperature (soldering, 10 seconds) Package body temperature (soldering, 2 minutes)
MIN -0.3V -0.3V DGND -0.3V AGND -0.3V 0C
o o o
MAX +7V +7V DVDD +0.3V AVDD +0.3V +70oC +150oC +240oC +183oC
30 C max / 85% RH max -65 C
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WM9709 DC ELECTRICAL CHARACTERISTICS
Test Conditions: o AVDD = 5V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = 25 C, unless otherwise stated. PARAMETER Supply Ranges Digital supply range Analogue supply range Digital ground Analogue ground Difference DGND to AGND Supply Currents Analogue supply current Analogue supply current Digital supply current Digital Logic Levels (DVDD = 3.3) Input LOW level Input HIGH level Output LOW Output HIGH VIL VIH VOL VOH ILOAD = 1mA ILOAD = 1mA 0.9 DVDD DGND - 0.3 0.75 DVDD DVDD=3.3V, AVDD = 5V DVDD, AVDD = 3.3V DVDD, AVDD = 3.3V 12.5 11 5 8 20 DVDD AVDD DGND AGND -0.3 -10% -10% 3.3 3.3 to 5.0 0 0 0 +0.3 +10% +10% SYMBOL TEST CONDITIONS MIN TYP MAX
Production Data
UNIT V V V V V mA mA mA V V V V
0.25 DVDD DVDD + 0.3 0.1 DVDD
AC ELECTRICAL CHARACTERISTICS
Test Conditions: AVDD = 5V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = 25oC, unless otherwise stated. PARAMETER Reference Levels Reference input/output CAP impedance DAC Circuit Specifications (48kHz Sample Rate) SNR A-weighted (Note 1,2) Dynamic Range Full scale output voltage into 10k load THD Channel Separation Channel Matching PSRR Output offset wrt CAP voltage Clock Frequency Range Crystal clock BITCLK frequency SYNC frequency 24.576 12.288 48.0 MHz MHz kHz 1kHz, 10F on CAP pin -30 DNR AVDD = 5V AVDD = 3.3V AVDD = 5V AVDD = 3.3V AVDD=5V AVDD=3.3V 0dBfs 95 -0.35 95 0.95 95 102 99 102 99 1.0 0.66 -95 102 0 46 0 30 0.35 -85 1.05 dB dB dB dB Vrms Vrms dB dB dB dB mV CAP AVDD/2 - 25mV AVDD/2 5 AVDD/2 + 25mV k SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
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Production Data
WM9709
Notes: 1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted over a 20Hz to 20kHz bandwidth. 2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. SNR measured with A-weight filter is typically 2dB better than with CCIR2k filter, or 20kHz low pass filter.
TERMINOLOGY
1. 2. 3. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Dynamic range (dB) - DNR is a measure of the ratio between the largest and smallest usable signals. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= 42dB, DNR= 102dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4.
SERIAL INTERFACE TIMINGS
Test Conditions: AVDD = 5V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = 25oC, unless otherwise stated. All measurements are taken at 10% to 90% VDD, unless otherwise stated. All the following timing information is guaranteed by design, but not tested in production.
COLD RESET
tRST_LOW RESETB tRST2CLK
BITCLK
Figure 1 Cold Reset Timing PARAMETER RESETB active low pulse width RESETB inactive to BITCLK startup delay SYMBOL tRST_LOW tRST2CLK MIN 1.0 162.8 TYP MAX UNIT s ns
WARM RESET
Not supported by WM9709
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WM9709
CLOCK SPECIFICATIONS
tCLK_HIGH BITCLK tCLK_LOW
Production Data
tCLK_PERIOD tSYNC_HIGH tSYNC_LOW
SYNC tSYNC_PERIOD
Figure 2 Clock Specifications (50pF External Load)
Note: Worst case duty cycle restricted to 40/60.
PARAMETER
BITCLK frequency BITCLK period BITCLK output jitter BITCLK high pulse width BITCLK low pulse width SYNC frequency SYNC period SYNC high pulse width SYNC low pulse width
SYMBOL
tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSYNC_HIGH tSYNC_LOW
MIN
TYP
12.288 81.4
MAX
UNIT
MHz ns
750 32.56 32.56 40.7 40.7 48.0 20.8 1.3 19.5 48.84 48.84
ps ns ns kHz s s s
DATA OUTPUT AND INPUT TIMES
tCO tSETUP
BITCLK tHOLD
SYNC, SDATAOUT, SDATAIN
Figure 3 Data Output and Input Timing
PARAMETER
Setup to falling edge of BITCLK Hold from falling edge of BITCLK Output Valid Delay from rising edge of BITCLK
SYMBOL
tSETUP tHOLD tCO
MIN
10.0 10.0
TYP
MAX
UNIT
ns ns
15.0
ns
ATE IN CIRCUIT TEST MODE
When the WM9709 is placed in the ATE test mode, its digital AC-link outputs (BITCLK and SDATAIN) are driven to a high impedance state. This allows ATE in circuit testing of the WM9709.
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Production Data
tsetup2rst RESETB
WM9709
SDATAOUT toff Hi-Z
SDATAIN, BITCLK
Figure 4 ATE Test Mode Timing PARAMETER
Setup to trailing edge of RESETB (also applies to SYNC) Rising edge of RESETB to Hi-Z delay
SYMBOL
Tsetup2rst Toff
MIN
15.0 -
TYP
-
MAX
25.0
UNIT
nS nS
Notes:
1. All WM9709 signals are normally low through the trailing edge of RESETB. Bringing SDATAOUT high for the trailing edge of RESETB causes WM9709's AC-link outputs to go high impedance, which is suitable for ATE in circuit testing. A vendor specific internal test mode can be entered by bringing SYNC high for the trailing edge of RESETB. This mode has no effect on WM9709 AC-link output signal levels. Once either of the two test modes have been entered, WM9709 must be issued another RESETB with all AC-link signals low to return to the normal operating mode.
2. 3.
SIGNAL RISE AND FALL TIMES
triseCLK BITCLK triseSYNC SYNC triseDIN SDATAIN triseDOUT SDATAOUT tfallDOUT tfallDIN tfallSYNC tfallCLK
Figure 5 Signal Rise and Fall Times (50pF external load)
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WM9709
PARAMETER
BITCLK rise time BITCLK fall time SYNC rise time SYNC fall time SDATAIN rise time SDATAIN fall time SDATAOUT rise time SDATAOUT fall time
Production Data
SYMBOL
triseCLK tfallCLK triseSYNC tfallSYNC triseDIN triseDIN triseDOUT tfallDOUT
MIN
2 2 2 2 2 2 2 2
TYP
MAX
6 6 6 6 6 6 6 6
UNIT
ns ns ns ns ns ns ns ns
DIGITAL FILTER RESPONSE
The WM9709 digital filter response is guaranteed by design but is not tested in production.
PARAMETER
Passband Stopband Passband ripple Stopband Attenuation
SYMBOL
TEST CONDITIONS
0.05 dB -3dB f > 0.555fs
MIN
0.444fs
TYP
0.487fs 0.05
MAX
UNIT
dB dB
-60
dB
TERMINOLOGY
1. 2. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside the audio band). Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
0.2 0 0.15 -20 0.1
Response (dB)
Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-100
-0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
-120
Figure 6 Digital Filter Frequency Response - 48kHz
Figure 7 Digital Filter Ripple - 48kHz
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Production Data
WM9709
DEVICE DESCRIPTION
INTRODUCTION
WM9709 contains a minimal subset of a revision 1.03 AC'97 compliant audio codec. WM9709 comprises a stereo 20-bit DAC and an Intel revision 1.03 AC-link compatible interface. No internal volume control stages, mute function or power down registers are provided. Vendor ID data may be read back from registers 7C and 7E. The SDATAIN output pin is used for outputting digital signals during manufacturing test, but does not output signals in normal operation. The DACs on WM9709 are implemented using a multi-bit switched capacitor sigma delta architecture which gives inherently low out of band noise and reduced clock jitter sensitivity. An internally generated mid-rail reference is provided at pin CAP which is used as the chip reference. This pin should be heavily de-coupled. See Figure 11.
CONTROL AND DATA INTERFACE
A digital interface to control and transfer to and from the WM9709 has been provided. This serial interface is compatible with the Intel revision 1.03 AC-link specification. The main control interface functions are: * * * Transfer of DAC words from AC-link controller. Control of test modes. Readback of vendor ID.
AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL
WM9709 incorporates a 5 pin digital serial interface that links it to the AC-link controller. The AC-link is a bi-directional, fixed rate, serial PCM digital stream. It handles multiple input, and output audio streams, as well as control register accesses employing a time division multiplexed (TDM) scheme. The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. WM9709 provides support for up to 20-bit operation of outgoing DAC data only. No incoming data is provided other than readback of vendor ID. A read request to any address other than 7C or 7E will respond with all 0s.
SLOT #
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
OUTGOING STREAMS
TAG
CMD ADR
CMD DATA
PCM LEFT
PCM RIGHT
OPT MDM CDC
CENTR ER
LSURR
RSURR
LFE
RSRVD
RSRVD
RSRVD
INCOMING STREAMS
TAG
CMD ADR
CMD DATA
PCM LEFT
PCM RIGHT
OPT MDM CDC
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
RSRVD
DATA PHASE TAG PHASE
Figure 8 AC-link Standard Bi-directional Audio Frame
Synchronisation of all AC-link data transactions is signaled by the WM9709 controller. When WM9709 operates as a master (ID = `lo', normal operation) WM9709 drives the serial bit clock BITCLK onto the AC-link, which the AC-link controller then qualifies with a synchronisation signal to construct audio frames. When a multi channel system is implemented using 2 or 3 WM9709 or other AC'97 devices, one of the AC link devices MUST be a master. Other WM9709 devices used as surround or centre/LFE channel devices (by selecting ID = high or `Z') act as slaves. In this case BITCLK is an input. The system clock is not required for slave devices, which use BITCLK for all internal functions. The BITCLK input is used for all internal filtering operations.
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WM9709
Production Data SYNC is fixed at 48 kHz, and is derived by the AC-link controller which divides down the serial clock (BITCLK). BITCLK, fixed at 12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. AC-link serial data is transitioned on each rising edge of BITCLK. The receiver of AC-link data, (WM9709 for SDATAOUT data), samples each serial bit on the falling edges of BITCLK. The AC-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A `1' in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is "tagged" invalid, WM9709 will ignore the corresponding data slot. SYNC remains high for a total duration of 16 BITCLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is high is defined as the "Tag Phase". The remainder of the audio frame where SYNC is low is defined as the "Data Phase". Additionally, for power savings, all clock, sync, and data signals can be halted.
AC-LINK AUDIO OUTPUT FRAME (SDATAOUT)
SDATAOUT, the audio frame data input to the WM9709, contains audio and control data time multiplexed onto one bus. As briefly mentioned earlier, each audio output frame supports up to 12, 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16-bits, which are used for AC-link protocol infrastructure. The first bit within slot 0 is a global bit (SDATAOUT slot 0, bit 15) which flags the validity for the entire audio frame. If the "Valid Frame" bit is a 1, this indicates that the current audio frame contains at least one time slot of valid data. The next 12-bit positions sampled by the WM9709 indicate which of the corresponding 12 time slots contain valid data.
WM9709 samples SYNC assertion here
SYNC BITCLK
WM9709 samples first SDATAOUT bit of frame here
SDATAOUT
Valid Frame
Slot (1)
Slot (2)
End of previous Audio Frame
Figure 9 Start of an Audio Output Frame
A new audio output frame begins with a low to high transition of SYNC as shown in Figure 7. SYNC is synchronous to the rising edge of BITCLK. On the immediately following falling edge of BITCLK, WM9709 samples the assertion of SYNC. This falling edge marks the time when both sides of the AC-link are aware of the start of a new audio frame. On the next rising edge of BITCLK, the AC-link controller transitions SDATAOUT into the first bit position of slot 0 ("Valid Frame" bit). Each new bit position is presented to AC-link on a rising edge of BITCLK, and subsequently sampled by the WM9709 on the following falling edge of BITCLK. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. Baseline AC'97 specified audio functionality MUST ALWAYS sample rate convert to and from a fixed 48 kS/s on the AC'97 controller. This requirement is necessary to ensure that interoperability between the AC-link controller and WM9709 can be guaranteed by definition for baseline specified AC'97 features. SDATAOUT's composite stream is MSB justified (MSB first) with all non-valid slot bit positions stuffed with 0s by the AC-link controller. As an example, consider an 8-bit sample stream that is being played out to one of WM9709's DACs. The first 8-bit positions are presented to the DAC (MSB justified) followed by the next 12-bitpositions, which are stuffed with 0s by the AC-link controller. This ensures that regardless of the resolution of the implemented DAC (16, 18 or 20-bit), the least significant bits will introduce no DC biasing.
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Production Data
WM9709
When mono audio sample streams are output from the AC-link controller, it is necessary that BOTH left and right sample stream time slots be filled with the same data.
SLOT 1: COMMAND ADDRESS PORT
Bit(19) Bit(18:12) Bit(11:0) Read/write command (1 = read, 0 = write) Control register index (64 16-bit locations, addressed on even byte boundaries) Reserved (stuffed with 0s)
The first bit (MSB) sampled by WM9709 indicates whether the current control transaction is a read or write operation. The following 7 bit positions communicate the targeted control register address. The trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the AC-link controller. In the case of the WM9709, read mode is required only to access the vendor ID register
SLOT 2: COMMAND DATA PORT
The Slot 2 command data port is not normally used by WM9709.
SLOTS 3 & 4: PCM PLAYBACK LEFT & RIGHT CHANNELS
Audio output frame slots 3 & 4 are the composite digital audio left and right playback streams. In a typical `Games Compatible' PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC-link controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC-link controller must stuff all trailing non-valid bit positions within this time slot with 0s. When WM9709 pin 2 (ID) is held low, data from slots 3 & 4 is mapped onto the DAC inputs.
SLOTS 5: OPTIONAL MODEM LINE CODEC
Audio output frame slot 5 would typically contain the MSB justified modem DAC input data. This optional AC'97 feature is not supported in WM9709, and data is ignored if written to this location.
SLOTS 6 & 9: PCM PLAYBACK CENTRE AND LFE CHANNELS
Audio data corresponding to surround centre and LFE channels is contained in slots 6 & 9. When pin 2 (ID) is left high impedance (not driven), data from these slots is mapped onto the DAC inputs. In this mode BITCLK is an input from the AC-link MASTER.
SLOTS 7 & 8: PCM PLAYBACK SURROUND LEFT & RIGHT CHANNELS
Audio data corresponding to surround left and right channels is contained in slots 7 & 8. When pin 2 (ID) is pulled high, data from these slots is mapped onto the DAC inputs. In this mode BITCLK is an input from the AC-link MASTER.
AC-LINK AUDIO INPUT FRAME (SDATAIN)
The audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC-link controller. As is the case for an audio output frame, each AC-link audio input frame consists of 12, 20-bit time slots. The WM9709 supports a reduced set of these audio input frames, specifically slots 0,1 and 2. The first bit within slot 0 is a global bit (SDATAIN slot 0, bit 15) which flags whether WM9709 is in the "DAC Ready" state or not. If the "DAC Ready" bit is a 0, this indicates that WM9709 is not ready for normal operation. When the AC-link "DAC Ready" indicator bit is a 1, it indicates that the AC-link and WM9709 control and status registers are in a fully operational state. Once WM9709 is sampled "DAC Ready" then the next 12 bit positions sampled by the AC-link controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. Figure 8 illustrates the time slot based AC-link protocol.
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WM9709
WM9709 SAMPLES SYNC ASSERTION
Production Data
SYNC BITCLK SDATAIN
AC-LINK CONTROLLER SAMPLES FIRST SDATAIN BIT OF FRAME
DAC READY
SLOT(1)
SLOT(2)
END OF PREVIOUS AUDIO FRAME
Figure 10 Start of an Audio Input Frame
SDATAIN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0's by the WM9709. SDATAIN is sampled on the falling edges of BITCLK.
SLOT 1: STATUS ADDRESS PORT
Audio input frame slot 1 echoes the control register index from the read request, for historical reference, for the data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged "valid" by WM9709 during slot 0).
STATUS ADDRESS PORT BIT ASSIGNMENTS:
Bit(19) Bit(18:12) Bit(11:0) RESERVED (stuffed with 0s) Control register index (echo of register index for which data is being returned) RESERVED (stuffed with 0s)
The first bit (MSB) generated by WM9709 is always stuffed with a 0. The following 7 bit positions communicate the associated control register address, and the trailing 12-bit positions are stuffed with 0s by WM9709
SLOT 2: STATUS DATA PORT
The status data port delivers 16-bit control register read data. Bit(19:4) Bit(3:0) Control register read data (stuffed with 0s if tagged "invalid" by WM9709) RESERVED (stuffed with 0s)
If slot 2 is tagged "invalid" by WM9709, then the entire slot will be stuffed with 0s. The WM9709 will use this port only to return the data value of the vendor ID.
SLOTS 3-12: UNUSED
The remaining slots in the audio input frame are not used by the WM9709. All bits in these slots will be stuffed with 0s.
AC-LINK LOW POWER MODE
Not supported by WM9709
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Production Data
WM9709
See Table 1. Only special production test modes and vendor ID readback are supported by the WM9709 register map. The test mode addresses are chosen to avoid conflict with any data that might be written to normal AC'97 register addresses. None of the typical AC'97 mixer, control, power up/down control functions are supported by the WM9709.
SERIAL INTERFACE REGISTER MAP DESCRIPTION
VENDOR RESERVED REGISTER (INDEX 5AH)
This register is reserved for future use and is vendor specific. Do not write to these registers unless the Vendor ID register has been checked first to ensure that the driver knows the source of the AC'97 component. Values stored in this register are used to provide test modes for the manufacturer.
VENDOR ID REGISTERS (INDEX 7Ch - 7Eh)
This register is for specific vendor identification if so desired. The ID method is Microsoft's Plug and Play Vendor ID code. The first character of that ID is F7 to F0, the second character S7 to S0 and the third T7 to T0. These three characters are ASCII encoded. The REV7 to REV0 field is for the Vendor Revision number. In the WM9709, the vendor ID is set to WML9.
SERIAL INTERFACE REGISTER MAP
The following table shows the function and address of the various control bits that are loaded through the serial interface during write operations.
Reg. Num. 5Ah 7Ch 7Eh Name Vendor Reserved Vendor ID1 Vendor ID2 D15 X F7 T7 D14 X F6 T6 D13 X F5 T5 D12 X F4 T4 D11 X F3 T3 D10 X F2 T2 D9 X F1 T1 D8 X F0 T0 D7 X S7 REV 7 D6 X S6 REV 6 D5 X S5 REV 5 D4 X S4 REV 4 D3 X S3 REV 3 D2 X S2 REV 2 D1 X S1 REV 1 D0 X S0 REV 0 Default X 574D 4CO9
Table 1 Serial Interface Register Map Description
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WM9709 RECOMMENDED EXTERNAL COMPONENTS
DVDD AVDD 3
C1 C2
Production Data
DVDD
AVDD
19
C3 C4
8 DGND DGND 2
AGND AGND
20 11 AGND
ID CAP 14
C5
C6
+
AGND LINEOUTL LINEOUTR 16 17
+ +
C7 C8
STEREO OUTPUT
6 7
SDATAOUT BITCLK SDATAIN SYNC RESETB XTLIN 4
XT C10 C9
NC 12 13 NC 15 NC 18 NC
AC-LINK
9 10 1
XTLOUT 5
DGND
Notes: 1. C1 to C5 should be as close to WM9709 as possible. 2. AGND and DGND should be connected as close to WM9709 as possible.
Figure 11 External Components Diagram
RECOMMENDED EXTERNAL COMPONENT VALUES
COMPONENT REFERENCE
C1 to C4 C5 C6 C7 to C8 C9 and C10 XT
SUGGESTED VALUE
0.1F + 1uF 0.1F 10F 10F 22pF 24.576 MHz
DESCRIPTION
De-coupling for DVDD and AVDD Reference de-coupling capacitors for DAC Output AC coupling caps to remove VREF DC level from outputs. Optional capacitors for better crystal frequency stability. WM9709 master clock frequency. A bias resistor is not required, but if connected will not affect operation if value is large (above 1M).
Table 2 External Component Recommendations
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Production Data
WM9709
The WM9709 device performance with AVDD = 3.3V is shown in Electrical Characteristics. The mid-rail reference is set to AVDD/2. The analogue full-scale output signal is 1Vrms centred at midrail for AVDD=5V. For AVDD=3.3V, the full-scale output is 660mV rms. If 1Vrms output is required, external gain must be increased.
RECOMMENDATIONS FOR 3.3V OPERATION
RECOMMENDATIONS FOR EXTERNAL FILTER
For undemanding applications, the output from WM9709 may be used without an external buffer. Typically a simple AC coupling cap of suitable value is used to remove the midrail DC pedestal from the audio signal, with a simple RC filter used to both protect the DAC and remove any residual high frequency RF noise which might appear at the outputs. An RC combination of series 1k resistor and 3.9nF to ground would suffice, and the resulting output impedance of 1k ohm is likely to be acceptable in many applications. In more demanding applications, such as DVD playback, more filtering and a lower output impedance are often required. Due to the use of a low order sigma delta modulator on WM9709, a second order filter may suffice. Additional filtering may not result in any significant noise reduction. This filter is normally implemented using an active stage, which can then be used to perform the function of increasing the output amplitude of the signal from the WM9709 from typically 1Vrms to the 2Vrms often specified for consumer digital audio equipment. Figure 12 shows an example of a typical 2nd order filter and buffer circuit that might be used. In this case the AC coupling capacitor that would typically be placed between the DAC output and the filter input has been removed in order that the DAC pedestal from the output of the DAC is maintained. This allows use of a single supply opamp, removing the need for a negative supply in the audio subsystem. The output signals now swing around the DC pedestal, the DC offset being removed by the AC coupling capacitor at the filter output.
RECOMMENDATIONS FOR MINIMISING POWER UP/DOWN `CLICKS'
Removal of power up/down clicks is typically required in consumer electronic equipment. The WM9709 is designed to minimise the start-up and shut down `click' when power is applied or removed or when the device is switched into or out of its reset mode of operation (RESETB state is changed). However, because the WM9709 DAC is followed typically by an active filter, power on/off clicks may still occur if this filter circuit is not carefully designed, and/or some form of `clamp' or `mute' circuit is not used at the output. There are two primary concerns when attempting to minimise `clicks'; one is the issue of charging the AC coupling capacitor in a controlled way and avoiding transients as the DC is established across it. The other is avoiding `clicks' when the output op-amp is powered up or down. The first point of charging the capacitor is addressed by providing a control pin to allow the DC at the DAC output to be ramped up or down by tying the DAC output to the CAP pin. This allows the user to choose the external capacitor value to set the time constant. This can minimise the resultant output transient, but it does this by giving it sub-audio characteristics, which may still cause problems in some systems. The second point of powering up and down the output stage opamp may or may not generate significant `clicks' depending on how the chosen opamp behaves at this time. Many opamps will exhibit gain inversion when their supply is taken very low. At that point the output typically flips up to the positive supply rail generating a significant output spike. If the choice of filter opamp is based on it being well behaved under these conditions, a non-economic component choice may have to be made. It is recommended therefore that the whole problem be removed by use of a clamp or mute transistor on the output of each channel, the transistor being turned on at start-up and shut down when required. The device could be either an appropriate series MOSFET in the signal line, or alternatively a bipolar transistor that clamps the output to ground when the supplies are not stable. Typically low VCESAT transistors are chosen for this function in order to minimise residual DC voltage across the clamp device. The base or gate drive to this device will typically be the OR combination of power supply indicator signals and mute signals from the digital controller. This allows the mute to be applied for example in the case of damaged discs which would otherwise have caused audible noise. PD Rev 1.3 February 2003 15
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WM9709
Production Data
+12V 1nF +12V
AC = 1Vrms DC = 2.5V
+
0.1uF 10uF
8.72K
18K
+
Output from WM9709
4.7uF
100R
AC = 2Vrms DC = 0V
220pF
AGND 2K2
Figure 12 Typical External Filter and Components
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_
2K2 270pF 10K
Clamp Signal
FMMT617
Optional clamp device for reducing power on/ off noise
PD Rev 1.3 February 2003 16
Production Data
WM9709
PACKAGE DIMENSIONS
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
DM0015.B
b
20
e
11
E1
E
1
10
GAUGE PLANE
D
A A2
A1 -C0.10 C
SEATING PLANE
c
L L1
0.25
Symbols A A1 A2 b c D e E E1 L L1 REF: MIN ----0.05 1.65 0.22 0.09 6.90 7.40 5.00 0.55 0
o
Dimensions (mm) NOM --------1.75 0.30 ----7.20 0.65 BSC 7.80 5.30 0.75 0.125 REF o 4 JEDEC.95, MO-150
MAX 2.0 ----1.85 0.38 0.25 7.50 8.20 5.60 0.95 8
o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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PD Rev 1.3 February 2003 17
WM9709 IMPORTANT NOTICE
Production Data
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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PD Rev 1.3 February 2003 18

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